Software specifications based on S-35710M hardware specifications are as follows.
【 H-CMP Architecture 】
The H-CMP Architecture of this product is shown in the figure below.
The S-35710M compares the timer register value and the value written to the wake-up register, and outputs a wake-up signal (interrupt signal = INT ) when the values match each other.
Wake-up register 3byte [s/bit] MSB first
Timer register 3byte [s/bit] MSB first
The operation of the Timer register and Wake-up register is shown in the figure below.
SCL clock frequency VDD = 1.8 V to 2.5 V min 0kHz max 400kHz
fig9. Timer register read frame format
fig10. Wake-up register write frame format
fig11. Wake-up register read frame format
fig11. Release of SDA frame format